Nothing can stop RISC-V

According to some technologists in the field, the RISC-V architecture looks set to become more common in high-performance computing (HPC), and may even become the dominant architecture.

Meanwhile, the European High Performance Computing Joint Organization (EuroHPC JU) has just announced a project to develop RISC-V-based HPC hardware and software, with plans to deploy future exascale and post-exascale systems based on the technology. level supercomputer.

RISC-V has been around as an open source instruction set architecture (ISA) for at least a decade, and actual silicon based on modified ISAs has entered the market in the past few years.

The appeal of this approach is that the architecture is not only free to use, but also extensible, which means that application-specific functionality can be added to a RISC-V CPU design, and by adding custom instructions to standard RISC Access -V group.

The latter could prove to be the driver of wider adoption of RISC-V in HPC, according to Aaron Potler, a distinguished engineer at Dell Technologies.

“The synergy and strength of the RISC-V community in HPC is growing, so there’s a really, really good opportunity for RISC-V to become more popular in HPC,” Potler said.

Speaking at the Dell HPC Community online event, Potler outlined the views of Dell’s Office of the Chief Technology and Innovation Officer.

He admits, however, that RISC-V hasn’t really had much success in HPC so far, mostly because it wasn’t originally designed with that purpose in mind, but “now there are some targets for HPC” because The business model it represents.

He somewhat draws a comparison to Linux, which, like RISC-V, started out as a small project but has grown in popularity due to its openness (as Potler admits, it’s also free to download and run ).

“Nobody thought at the time that Linux would run on some high-end computers.

When the TOP500 list came out in 1993, only one Linux system was on the list. Today, every system on the TOP500 list runs Linux. each of them. It’s been that way for several years,” he said.

If Linux wasn’t originally aimed at the HPC market, but was adopted because of its inherent advantages, the same could happen with RISC-V, if there are enough advantages, such as being an open standard.

“If that’s what the industry wants, then the community will make it work, it will make it happen,” Potler said.

He also compared it to the Arm architecture, which eventually propelled Fujitsu’s Fugaku supercomputer to the top of the TOP500 rankings, and was notable by extending the instruction set to support the 512-bit Scalable Vector Engine Unit in the A64FX processor. achieved this goal.

“So why shouldn’t RISC-V-based systems be number one on the TOP500 one day?” he asked.

Potler claims that work has been done on HPC-related RISC-V instruction and architectural extensions, especially those for vector processing and floating-point operations.

All of this means RISC-V has potential, but can it really make headway in HPC?

This space used to have systems of various processor architectures, but is now almost completely dominated by X86 and Arm?

“RISC-V does have the potential to become the architecture of choice for the HPC market,” said Roy Illsley, principal analyst at Omdia. “I think Intel is losing control of the overall market, and the HPC space is becoming more specialized.”

Illsley noted that the open-source nature of RISC-V means that any chipmaker can produce a RISC-V-based design without paying royalties or licensing fees, and that many silicon manufacturers and open-source operating systems support this.

Manoj Sukumaran, principal analyst for data center computing and networking at Omdia, agrees, saying RISC-V’s biggest advantage is that its non-proprietary architecture aligns well with countries’ technological sovereignty goals.

“High-performance computing capability is a strategic advantage for any nation and is an integral part of a nation’s scientific and economic progress.

No country wants to be in such a position, and this is driving the adoption of RISC-V,” he claimed.

According to Sukumaran, RISC-V is also a “very efficient and compelling instruction set architecture,” and it can be customized with additional instructions for specific computing needs, which also makes it agile.

The EuroHPC JU’s call for a partnership framework to develop RISC-V-based HPC hardware and software as part of an EU-wide ecosystem could be an impetus for sovereignty, or at least greater self-reliance.

An ambitious action plan to build and deploy exascale and post-exascale supercomputers based on the technology is expected to follow, according to EuroHPC JU.

It said in the announcement that the European Chip Act identifies RISC-V as one of the next-generation technologies that should guide investments to maintain and strengthen the EU’s leadership in research and innovation.

This will also strengthen the EU’s ability to design, manufacture and package advanced chips, and to turn them into manufactured goods.

Chip companies such as SiFive and Ventana already offer high-performance RISC-V designs, but these are typically either designs that customers can adopt and be manufactured by foundries such as TSMC, or available as chiplets that can be built with others to customize System on Chip (SoC), this is Ventana’s approach.

Creating a CPU design with custom instructions to accelerate a specific function is probably beyond the resources of most HPC sites, but perhaps not a large user group or forum.

However, the chiplet approach can somewhat reduce the risk of the project, said Andrew Buss, IDC’s senior research director for Europe.

“Instead of trying to do a single big CPU, you could assemble an SoC from small chips, get your CPU cores from somewhere, and I/O hubs and other functions from other places,” he said, though he added that it would take Standardized interfaces to link the chiplets together.

But Buss said that despite RISC-V’s potential, the software ecosystem is more important. “It doesn’t matter what the underlying microarchitecture is, as long as there is a sufficient ecosystem of applications and tool software to support it,” he said.

Potler agrees, saying, “One of the most critical parts of HPC success is the software ecosystem. Because we’ve all worked on software-secondary architectures, it’s been a very frustrating time, right?”

Developer tools, especially compilers, need to be “reliable, they need to be extensible, and they need to understand the ISA well to generate good code,” he said.

This also comes into play in defining custom instructions, as these require a profiler or some profiling tool to identify time-consuming code sequences in the application being used, and measure whether specialized instructions can speed up those codes.

“So if I take these instructions out, I need a simulator that can simulate this [new] instruction.

If I put it here and take the other instructions out, the first question is, is the answer correct? Then the other thing is: is it running enough to be worth it? “

Another important factor, Potler said, is whether the compiler can identify a code sequence in an application and replace it with custom instructions to improve performance.

“You’ll also see extensions to instruction set architectures that will provide performance benefits for current and future HPC applications, whatever they may be,” he added.

However, Buss cautions that even with a lot of interest in RISC-V, it will take time for users at the HPC site to get there.

“There’s nothing stopping RISC-V, but it will take time to develop the performance and power to the required levels,” he said, noting that it took more than a decade for the Arm architecture to reach a point where it was competitive in this space.

Intel also suffered a setback when it dropped support for the RISC-V architecture last month, after it became a key member of RISC-V International, the standard’s governing body, and pledged to provide verification services for RISC-V IP cores targeting Intel fabs. ? Manufacturing has been optimized.

The text and pictures in this article are from Drive Home