After the domestic chip technology was “stuck” in 2018, many people who don’t pay attention to chips know a new word – EDA (Electronic Design Automation).
As the “jewel in the crown” of the semiconductor industry, EDA is also evolving with the development of the integrated circuit industry.
Interestingly, EDA verification tools have become a popular arena. In the past few years, many EDA startups have emerged in China, many of which have chosen the digital verification EDA arena.
Ling Lin, global vice president of Siemens EDA and general manager of China, believes that ” several foreign companies already have very strong EDA verification product lines, and domestic companies also choose to make efforts in the field of verification, which shows that everyone’s sense of smell is very sensitive. It is the bottleneck problem that needs to be solved at present. At this time, various solutions and new ideas will come out, which is a very good arena.”
As one of the three major EDA companies in the world, Siemens EDA has also recently launched a mixed-signal verification platform that can improve the verification efficiency of “sandwich” structure chips by an order of magnitude.
What is the logic behind EDA companies competing in the verification arena?
Verify the logic behind EDA becoming a popular arena
“Simulation and verification are of great concern because the circuit complexity and scale of the design are getting larger and larger, and chip designers are faced with technical challenges and resource challenges.” Ling Lin said.
Li Liji, general manager of Siemens EDA Asia Pacific Technology, also said, “The scale of chips is getting bigger and bigger, and the requirements for the methodology of solving chip design challenges are getting higher and higher, and traditional EDA software simulation is already facing a bottleneck.”
The more central challenge behind the bottlenecks faced by EDA verification software is economics, or cost-effectiveness.
In the history of semiconductor development, this is not a new problem. With the development of Moore’s Law, more and more transistors are integrated in a chip of the same area, the area of a single chip will become larger and larger, the functions will become more and more complex, and the cost of testing will also increase.
“The increase in testing cost is because the damage rate will also increase as the chip becomes larger, which requires increasing the time for the chip to be tested on the testing machine, and the cost of using the testing machine is calculated based on the usage time.” Ling Lin said, “Before the , Siemens EDA has developed a test vector compression technology, which greatly compresses the test vectors, compressing as much as 1,000 times, and greatly reduces the cost of chip testing.”
When the industry finds that technological innovation can solve problems, it naturally stimulates innovation in this field.
Of course, there is a cost-benefit factor that cannot be ignored with the many innovations in EDA verification tools today.
As the semiconductor process evolves, the design and manufacturing costs of a single chip are also getting higher and higher, and EDA verification tools are more important. A chip verification tool, which also brings a larger market space.
Mixed-signal chip verification efficiency increased by 10 times
The Symphony Pro platform, launched by Siemens EDA this month, is a simulation platform that can accelerate mixed-signal verification with an order of magnitude improvement in efficiency.
Mixed-signal includes both analog and digital signals, and with the development of 5G, next-generation vehicles, etc., the design of mixed-signal SoCs is becoming more and more popular. For example, 5G massive MIMO radios integrate analog signal chains with digital front ends (DFEs), image sensors combine analog pixel readout circuits with digital image signal processing, and digital RF sampling data converters in radar systems.
The advantage of mixed-signal circuits is that they help chips reduce power consumption, area, and cost, while improving performance.
Symphony Pro, which focuses on hybrid simulation, is an upgraded version of the previously launched Symphony platform. It is also important to achieve a 10-fold increase in efficiency due to the methodology.
Li Liji introduced that Symphony Pro not only supports the industry-standard Universal Verification Methodology (UVM), which can meet the challenges faced by large chip designs, but also supports the Unified Power Format (UPF), which drives the rapid deployment of low-power technologies and extends to the mixed-signal domain. Provides fast simulation capabilities in a unified environment for exceptional throughput and capacity.
” Symphony Pro can also support sandwich architecture, which means that traditional chips may alternately integrate multiple layers of analog and digital chips to support complex mixed-signal chips.” Li Liji further said.
Customer feedback is the best description of the actual experience of the product. Stephane Vivien, Senior CAD Manager, Imaging Business Unit at STMicroelectronics, said: “We participated in the early access program of Symphony Pro, and the advanced debugging capabilities and seamless support for multi-layer sandwich structures in Symphony Pro can help us greatly improve production efficiency.”
Jayanth Shreedhara, Senior CAD Manager at Silicon Labs, said, “Symphony Pro Visualizer mixed-signal technology has accelerated the debug turnaround time of our digitally top-level UVM test suite, reducing our verification time from days to hours, significantly improving productivity while increasing productivity. The coverage rate has converged.” Leifeng.com
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